NVIDIA的丹佛处理器，全美达呀全美达

http://blogs.nvidia.com/blog/201 ... 64-bit-for-android/

一个VLIW顺序处理器，又一个安腾。看来很久以前大牛们的猜测没错。
In other words, it is an in-order VLIW core with a dynamic recompiler ARM emulator in firmware. Like the old "x86" chips from Transmeta. Interesting design choice, we'll see how well it works in practice.

The Denver chip will use in-order control logic...... Mind blown- I applaud nvidia engineers!

this reduces the need to re-optimize the software routines. Instead of using hardware to extract the instruction-level parallelism (ILP) inherent in the code, Denver extracts the ILP once via software techniques, and then executes those routines repeatedly, thus amortizing the cost of ILP extraction over the many execution instances.

As part of the Dynamic Code Optimization process, Denver looks across a window of hundreds of instructions and unrolls loops, renames registers, removes unused instructions, and reorders the code in various ways for optimal speed. This effectively doubles the performance of the base-level hardware through the conversion of ARM code to highly optimized microcode routines and increases the execution energy efficiency.

The slight overhead of the dynamic optimization process is outweighed by the performance gains of already having optimized code ready to execute. In cases where code may not be frequently reused, Denver can process those ARM instructions di

- See more at: http://blogs.nvidia.com/blog/201 ... thash.Boe8Ju5N.dpufhttp://blogs.nvidia.com/blog/201 ... 64-bit-for-android/

一个VLIW顺序处理器，又一个安腾。看来很久以前大牛们的猜测没错。
In other words, it is an in-order VLIW core with a dynamic recompiler ARM emulator in firmware. Like the old "x86" chips from Transmeta. Interesting design choice, we'll see how well it works in practice.

The Denver chip will use in-order control logic...... Mind blown- I applaud nvidia engineers!

this reduces the need to re-optimize the software routines. Instead of using hardware to extract the instruction-level parallelism (ILP) inherent in the code, Denver extracts the ILP once via software techniques, and then executes those routines repeatedly, thus amortizing the cost of ILP extraction over the many execution instances.

As part of the Dynamic Code Optimization process, Denver looks across a window of hundreds of instructions and unrolls loops, renames registers, removes unused instructions, and reorders the code in various ways for optimal speed. This effectively doubles the performance of the base-level hardware through the conversion of ARM code to highly optimized microcode routines and increases the execution energy efficiency.

The slight overhead of the dynamic optimization process is outweighed by the performance gains of already having optimized code ready to execute. In cases where code may not be frequently reused, Denver can process those ARM instructions di

- See more at: http://blogs.nvidia.com/blog/201 ... thash.Boe8Ju5N.dpuf