高可靠容错MIL-STD-1553A/B总线控制器IP核

FBIP1553FT
——高可靠容错MIL-STD-1553A/B总线控制器IP核
1.遵循MIL-STD-1553A/B标准，支持MIL-STD-1553A/B规定的全部协议
2.可由软件配置为BC、BM或者RT
3.寄存器操作同BU6158X完全兼容
4.采用容错设计，大大提高总线控制器可靠性
可纠正存储器中出现的一位数据错误，检测两位数据错误；
寄存器采用TMR设计，可容忍一位寄存器翻转；
在存储器出现2位或者2位以上数据位错误时，控制器自动返回到安全状态，确保不发送错误数据。
5.标准异步总线接口，支持8位、16位总线宽度
6.专用复位引脚，用以在收到复位模式命令时，复位计算机系统
7.支持ALTERA cyclone系列和ACTEL proASIC系列FPGA
8.通用总线收发器接口，支持通用总线收发器芯片。
9.提供标准速率（1Mbps）版本和增强速率（10Mbps）版本

FBIP1553FT-high reliability fault tolerant MIL-STD-1553A/B bus controller IP core
1.Conform to MIL-STD-1553A/B standard, support full MIL-STD-1553A/B protocol
2.Integrates all the 3 type of bus device, could be configured as single BC, BM or RT
3.Register operation compatible with DDC BU6158x
4.Designed with fault-tolerant scheme, high-reliability assured
Correct 1-bit data error and detect 2-bit data error;
All the internal registers are designed with TMR, each register could tolerant “Single Event Upset”
Controller would stay in safe mode, when an uncorrectable error detected
5.Standard parallel memory bus interface, supports 8-bit and 16-bit bus width
6.Dedicated “reset” pin,asserted when “reset” mode command received
7.ALTERA cyclone and ACTEL proASIC FPGA supported
8.General transceiver interface, support general 1553B bus transceiver
9.Two bit rate version provided, normal bit rate(1Mbps) and enhanced bit rate(10Mbps) versionFBIP1553FT
——高可靠容错MIL-STD-1553A/B总线控制器IP核
1.遵循MIL-STD-1553A/B标准，支持MIL-STD-1553A/B规定的全部协议
2.可由软件配置为BC、BM或者RT
3.寄存器操作同BU6158X完全兼容
4.采用容错设计，大大提高总线控制器可靠性
可纠正存储器中出现的一位数据错误，检测两位数据错误；
寄存器采用TMR设计，可容忍一位寄存器翻转；
在存储器出现2位或者2位以上数据位错误时，控制器自动返回到安全状态，确保不发送错误数据。
5.标准异步总线接口，支持8位、16位总线宽度
6.专用复位引脚，用以在收到复位模式命令时，复位计算机系统
7.支持ALTERA cyclone系列和ACTEL proASIC系列FPGA
8.通用总线收发器接口，支持通用总线收发器芯片。
9.提供标准速率（1Mbps）版本和增强速率（10Mbps）版本

FBIP1553FT-high reliability fault tolerant MIL-STD-1553A/B bus controller IP core
1.Conform to MIL-STD-1553A/B standard, support full MIL-STD-1553A/B protocol
2.Integrates all the 3 type of bus device, could be configured as single BC, BM or RT
3.Register operation compatible with DDC BU6158x
4.Designed with fault-tolerant scheme, high-reliability assured
Correct 1-bit data error and detect 2-bit data error;
All the internal registers are designed with TMR, each register could tolerant “Single Event Upset”
Controller would stay in safe mode, when an uncorrectable error detected
5.Standard parallel memory bus interface, supports 8-bit and 16-bit bus width
6.Dedicated “reset” pin,asserted when “reset” mode command received
7.ALTERA cyclone and ACTEL proASIC FPGA supported
8.General transceiver interface, support general 1553B bus transceiver
9.Two bit rate version provided, normal bit rate(1Mbps) and enhanced bit rate(10Mbps) version